The present invention is generally directed to a method for forming structures exhibiting a high degree of planarity in metal oxide semiconductor field effect transistors (MOSFETs). More particularly, the present invention is directed to a method for preventing deposition of source/drain contact material on conductive gate line patterns.
In the fabrication of very large scale integrated circuits (VLSI), it is desirable to be able to fabricate device structures as small as possible in order to maximize the number of active devices which may be disposed on a single integrated circuit chip. Scaling down of VLSI devices not only requires miniaturization of device features, but also requires the use of multilevel interconnections. Furthermore, the greater the need and number for multilevel connections, the greater becomes the necessity for providing planar device structures. The planarity requirement is a consequence of the difficulty of providing step coverage over highly non-planar features. Step coverage problems contribute to lower device yield during manufacture, poor device parameters and a greaer proclivity for failure during operation. Accordingly, it is seen that it is very desirable to provide planar device structures.
Since a large portion of the active area in an FET device is consumed by source and/or drain contacts, it becomes increasingly difficult to scale down the contact size without proportionally affecting gate dimensions. In this regard, it is to be generally noted that scaling device features as measured in square area units cannot generally be undertaken without also affecting height dimensions of circuit features. This is a direct consequence of the etching and lithography processes employed in the fabrication of VLSI devices.
With particular reference to problems solved by the present invention, it is to be noted that FET gate thickness should also be decreased to facilitate multilevel interconnection. It is therefore seen that it is desirable that gate electrode material not extend in height beyond the level generally associated with the field oxide region.
One of the methods employed to decrease device size is the utilization of selective chemical vapor deposition of metal on material comprising the active region of an FET device. However, chemical vapor deposited metal also is deposited on conductive gate structures comprising materials such as polycrystalline silicon or molybdenum. This increases gate height and produces an adverse effect on the desired planar structure. Also, in particular reference to the present invention, it is to be noted that molybdenum is a desirable metal for use as gate electrode material because of its low electrical resistivity and its mechanical properties which closely match those of silicon and related semiconductor materials, particularly with respect to its coefficient of thermal expansion.